1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device. More particularly, it relates to a defective column management technique of an electrically rewritable nonvolatile semiconductor storage device.
2. Description of the Related Art
Heretofore, as one of electrically rewritable nonvolatile semiconductor storage devices, a NAND flash memory is known. In the NAND flash memory, in order to repair a defect of a memory cell generated during manufacturing steps, a redundant column repair system (flexible column-redundancy) is incorporated in the NAND flash memory, which automatically replaces a defective column with a redundant column. In the redundant column repair system, it is detected whether or not an input column address coincides with a defective column address. When the input column address coincides with the defective column address, a column to be accessed is changed (e.g., see Jpn. Pat. Appln. KOKAI Publication No. 2001-250395).
In a defect address storage circuit, a fuse circuit or a ROM circuit is usually used. However, another system including no such a circuit has been proposed, in which a defect address is stored together with other various initial setting data in a memory cell array (e.g., see Jpn. Pat. Appln. KOKAI Publication No. 2001-176290). In this case, when power supply is turned on, the defect address is automatically read out and transferred to an initial setting register. In the subsequent operation, replacement of the defective column is carried out based on the defect address held in the initial setting register.
Moreover, in a data write sequence in the NAND flash memory, write potential application and write verification are repeatedly performed. That is, after verification reading, verification judgment (pass/failure judgment) is performed to check whether or not the writing of all the data has been completed. In a case where it is judged that the writing of all the bits has been completed, the write sequence ends. In a case where it is judged that an insufficiently written bit is present, the write potential is applied again.
A maximum number Nmax of the application times of the write potential (a write cycle number or a loop number) is preset. Even in a case where the number of writes reaches Nmax, when the writing of all the bits does not end, the write is regarded as a “failure”, so that the write sequence ends.
When the verification judgment is performed on a column including a defective memory cell, the writing is repeated until the number of writing reaches the maximum number Nmax, since the writing of the defective memory cell is not completed. After the writing of the maximum number Nmax, the judgment results in the “failure”. Therefore, time for the write sequence increases. To solve the problem, there has been a further proposal in which a verification judgment circuit is provided with a latch circuit to hold data for separating the defective column and in which the defective column is excluded from a judgment target of the verification judgment (e.g., see Jpn. Pat. Appln. KOKAI Publication No. 2002-140899).
Furthermore, there has been a further proposal including a latch circuit to which defective column separation data can be written in accordance with a command input from the outside a semiconductor chip in order to repair the NAND flash memory from a defect generated during use of the memory (e.g., see Jpn. Pat. Appln. KOKAI Publication No. 2006-79695).
In the redundant column repair system, however, a comparison circuit provided in the NAND flash memory detects whether or not the input column address agrees with the defective column address every time required, and the replacement for changing the column to be accessed is performed. This is a factor disturbing a high-rate operation.
Moreover, in a case where no defective column is present in the memory device, or only defective columns fewer than the pre-mounted redundant columns are present, the device is shipped with the unused redundant columns. In this case, although the columns are normal as memory cells, an unused area where data cannot be written from the outside or inside of the chip is present. This cannot be recognized that the memory cells are effectively used, which reduces convenience.